With advances in technology and the miniaturization of device elements in semiconductor integrated circuits, integrated circuits are becoming more susceptible to damage due to electrostatic discharge (ESD). In many applications, device elements have reached the submicron level in size, and correspondingly, MOS gate oxide films have become increasingly thin. As a result, the internal circuitry of an integrated circuit device is easily damaged by an ESD event. As semiconductors continue to shrink in size and become increasingly more complex, significant Electrical Overstress (EOS) and Electrostatic Discharge (ESD) become a greater challenge for both designers and manufacturers.
Electrical overstress (EOS) is a thermal overstress event that is introduced when a product is exposed to a current or voltage beyond its maximum rating, usually from power supplies or test equipment. The duration of EOS events ranges from milliseconds to seconds (typical >50 μsec). An EOS failure is typically catastrophic and causes permanent, irreparable damage to the integrated circuit device. An ESD event is a transfer of electrostatic charge between bodies or surfaces at different electrostatic potentials, either through direct contact or through induced electrical fields. ESD is considered to be a subset of EOS and is usually caused by static electricity. The duration of ESD events ranges from nanoseconds to microseconds.
Protection circuits are known in the art for protecting the circuitry of an integrated circuit from EOS and ESD event damage. It is known in the art to employ an active clamp with an R-C sense for ESD protection. With this system, an R-C sensing element formed by a capacitor and a resistor is used to sense the ESD pulse and actively drive the gate of a clamping transistor through an inverter. With the clamping transistor turned on, the excess voltage is shunted to ground and the core circuitry is protected from the ESD pulse. The clamping transistor will remain conductive for a period of time which is determined by the RC time constant of the trigger circuit. As a result, this RC time constant should be set long enough to exceed the maximum expected duration of an ESD event, typically three to five hundred nanoseconds, while short enough to avoid false triggering of the clamp circuit during normal ramp-up of the VDD power rail. This VDD ramp-up during normal operation typically requires two to five milliseconds. Note that once VDD reaches a constant power supply level, the circuit is biased in a nonconductive state as required for normal operation. It is also known in the art to replace the resistor in the R-C sensing element with a transistor, such as a grounded-gate p-channel transistor.
While such an active ESD-protection circuit is useful, it may be susceptible to noise, especially during power-up of the chip. If the active ESD-protection circuit triggers during power-up, the quick turn off of the ESD clamping device may cause a power bus overshoot or undershoot. The stress on the circuitry results from this overshoot or undershoot voltage can damage the ESD-protection circuit during power-up and cause power shorting through the damaged device.
In light of the above, a need exists in the art for an active ESD-protection circuit that prevents an overshoot or undershoot condition when the ESD-protection circuit is unintentionally triggered during power-up of the integrated circuit.